The present invention relates to data processing circuits, and in particular to a Direct Memory Access (DMA) controller operative to maintain and store a transfer count.
DMA operations are well known in the art. A DMA controller operates to offload routine data transfer tasks from a processor or other system controller. In an exemplary DMA transfer operation, a processor initializes the DMA controller with source and target information, control information, and a transfer size. The DMA controller autonomously reads data from the source, which may comprise a peripheral, such as a communication interface, or a memory location, and writes the data to the target, which may also comprise a peripheral or memory. Accordingly, the DMA transfer may be from a peripheral to a peripheral, peripheral to memory, memory to peripheral, or memory to memory. The DMA controller typically stores the transfer size in a counter, and decrements it upon writing each datum (e.g., byte, halfword, etc.). When the transfer size has decremented to zero, the DMA transfer operation is complete, and the DMA controller may interrupt the processor, set a flag in a status or control register, or otherwise indicate completion of the data transfer. A multi-channel DMA controller performs two or more DMA transfer operations in parallel, typically by time-division multiplexing the DMA transfers.
DMA transfer operations may be linked. For example, a very large data transfer may be broken into a sequence of smaller transfers. The DMA controller may be initialized with source, target, transfer size, and other control information, and may additionally be provided a linking address. When the DMA controller completes the DMA transfer, it reads a new set of source, target, transfer size, and control information from the linking address, as well as a new linking address, and immediately begins a new DMA transfer operation. In this manner, a large number of DMA transfer operations may be linked, or chained, together to move large amounts of data.
In many cases, the length of a DMA transfer is not known in advance. For example, a DMA transfer from a communication peripheral to memory may transfer one or more packets, whose length is not known prior to receipt at the peripheral. Additionally, DMA transfers of a nominally known length may terminate prematurely, such as if a peripheral times out, or if a destination buffer fills. In either case, software needs to ascertain the amount of data transferred to be able to process the data. In conventional DMA controllers, the transfer count (either incremented from zero or decremented from a nominal transfer count) must be read by the processor prior to the DMA controller beginning a subsequent DMA transfer, which will overwrite the DMA transfer count register or counter.
Even if the DMA controller interrupts the processor when the DMA transfer operation terminates, the context switch required for the processor to halt execution, load an interrupt service routine, and read the DMA transfer count—thus releasing the DMA controller to perform a subsequent DMA transfer operation—requires a large and in many cases unacceptable delay. As computing systems increase in functionality and complexity, the number of peripherals sharing data, the amount of data to be transferred, and system data rates all increase, reducing the maximum acceptable delay between DMA transfer operations. Accordingly, a need exists in the art to “decouple” the processor from the DMA controller in the case of DMA transfers of unknown size.